Electrical overstress (EOS) (Record no. 116894)
| 000 -LEADER | |
|---|---|
| fixed length control field | 03701nam a2200361 a 4500 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815 |
| 100 1# - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Voldman, Steven H. |
| 245 10 - TITLE STATEMENT | |
| Title | Electrical overstress (EOS) |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | Chichester, West Sussex, U.K. : |
| Name of publisher | John Wiley & Sons Inc., |
| Year of publication | 2014. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | xxiv, 344 p. : |
| Other physical details | ill. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | "Electrical Overstress (EOS) continues to impact semiconductor manufacturing, semiconductor components and systems as technologies scale from micro- to nano-electronics. This bookteaches the fundamentals of electrical overstress and how to minimize and mitigate EOS failures. The text provides a clear picture of EOS phenomena, EOS origins, EOS sources, EOS physics, EOS failure mechanisms, and EOS on-chip and system design. It provides an illuminating insight into the sources of EOS in manufacturing, integration of on-chip, and system level EOS protection networks, followed by examples in specific technologies, circuits, and chips. The book is unique in covering the EOS manufacturing issues from on-chip design and electronic design automation to factory-level EOS program management in today's modern world.Look inside for extensive coverage on: Fundamentals of electrical overstress, from EOS physics, EOS time scales, safe operating area (SOA), to physical models for EOS phenomena EOS sources in today's semiconductor manufacturing environment, and EOS program management, handling and EOS auditing processing to avoid EOS failures EOS failures in both semiconductor devices, circuits and system Discussion of how to distinguish between EOS events, and electrostatic discharge (ESD) events (e.g. such as human body model (HBM), charged device model (CDM), cable discharge events (CDM), charged board events (CBE), to system level IEC 61000-4-2 test events) EOS protection on-chip design practices and how they differ from ESD protection networks and solutions Discussion of EOS system level concerns in printed circuit boards (PCB), and manufacturing equipment Examples of EOS issues in state-of-the-art digital, analog and power technologies including CMOS, LDMOS, and BCD EOS design rule checking (DRC), LVS, and ERC electronic design automation (EDA) and how it is distinct from ESD EDA systems EOS testing and qualification techniques, and Practical off-chip ESD protection and system level solutions to provide more robust systems Electrical Overstress (EOS): Devices, Circuits and Systems is a continuation of the author's series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the nano-electronic era"-- |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Semiconductors |
| Topical Term | Semiconductors |
| Topical Term | Transients (Electricity) |
| Topical Term | Overvoltage. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://site.ebrary.com/lib/rucke/Doc?id=10753372 |
| 520 ## - SUMMARY, ETC. | |
| -- | Provided by publisher. |
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