01395nam a2200337Ia 4500001001200000003000800012006001900020007001500039008004100054020001800095020001500113040002100128035002100149050002400170082001800194100002800212245014500240260003500385300002300420490004800443504005100491533015200542650003400694650005000728650002900778655002900807700002900836710001700865830004900882856012600931ebr10412729CaPaEBRm        u        cr cn|||||||||091005s2010    maua    sb    001 0 eng d  z9781596939899  z1596939893  aCaPaEBRcCaPaEBR  a(OCoLC)67229363914aTK7874b.B35 2010eb04a621.381322221 aBahukudumbi, Sudarshan.10aWafer-level testing and test during burn-in for integrated circuitsh[electronic resource] /cSudarshan Bahukudumbi, Krishnendu Chakrabarty.  aBoston :bArtech House,c2010.  axv, 198 p. :bill.1 aArtech House integrated microsystems series  aIncludes bibliographical references and index.  aElectronic reproduction.bPalo Alto, Calif. :cebrary,d2011.nAvailable via World Wide Web.nAccess may be limited to ebrary affiliated libraries. 0aIntegrated circuitsxTesting. 0aIntegrated circuitsxWafer-scale integration. 0aSemiconductorsxTesting. 7aElectronic books.2local1 aChakrabarty, Krishnendu.2 aebrary, Inc. 0aArtech House integrated microsystems series.40uhttp://site.ebrary.com/lib/rucke/Doc?id=10412729zAn electronic book accessible through the World Wide Web; click to view