Your search returned 8 results.

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Hybrid parallel execution model for logic-based specification languages by Tsai, Jeffrey J.-P. Publication: Singapore ; | New Jersey : World Scientific, 2001 . xii, 214 p. : Date: 2001 Availability: No items available:

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Hybrid parallel execution model for logic-based specification languages by Tsai, Jeffrey J.-P. Publication: Singapore ; | New Jersey : World Scientific, 2001 . xii, 214 p. : Date: 2001 Availability: No items available:

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CTL for test information of digital ICs by Kapur, Rohit. Publication: Boston : Kluwer Academic Publishers, 2003 . ix, 173 p. : Date: 2003 Availability: No items available:

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Writing testbenches functional verification of HDL models / by Bergeron, Janick. Publication: New York : Kluwer Academic, 2002 . xxii, 354 p. : , Includes index. Date: 2002 Availability: No items available:

7.
CTL for test information of digital ICs by Kapur, Rohit. Publication: Boston : Kluwer Academic Publishers, 2003 . ix, 173 p. : Date: 2003 Availability: No items available:

8.
Writing testbenches functional verification of HDL models / by Bergeron, Janick. Publication: New York : Kluwer Academic, 2002 . xxii, 354 p. : , Includes index. Date: 2002 Availability: No items available:

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