Rongo Univesity Library catalog › Results of search for 'ccl=su:Integrated circuits and su:Testing.'

	1.	No cover image available RF measurements for cellular phones and wireless data systems by Scott, Allan W. Publication: Hoboken, N.J. : IEEE : \| Wiley & Sons, 2008 . xx, 503 p. : Date: 2008 Availability: No items available: Add to cart (remove)
	2.	No cover image available Power-constrained testing of VLSI circuits by Nicolici, Nicola. Publication: Boston : Kluwer Academic Publishers, 2003 . xi, 178 p. : Date: 2003 Availability: No items available: Add to cart (remove)
	3.	No cover image available CTL for test information of digital ICs by Kapur, Rohit. Publication: Boston : Kluwer Academic Publishers, 2003 . ix, 173 p. : Date: 2003 Availability: No items available: Add to cart (remove)
	4.	No cover image available ESD failure mechanisms and models / by Voldman, Steven H. Publication: Chichester, West Sussex, U.K. ; \| Hoboken, NJ : J. Wiley, 2009 . xxiv, 384 p. Date: 2009 Availability: No items available: Add to cart (remove)
	5.	No cover image available Design for at-speed test, diagnosis, and measurement Publication: Boston : Kluwer Academic, 2000 . xvii, 239 p. : Date: 2000 Availability: No items available: Add to cart (remove)
	6.	No cover image available Essentials of electronic testing for digital, memory, and mixed signal VLSI circuits by Bushnell, Michael L. Publication: New York : Kluwer Academic, 2002 . xviii, 690 p. : Date: 2002 Availability: No items available: Add to cart (remove)
	7.	No cover image available Wafer-level testing and test during burn-in for integrated circuits by Bahukudumbi, Sudarshan. Publication: Boston : Artech House, 2010 . xv, 198 p. : Date: 2010 Availability: No items available: Add to cart (remove)
	8.	No cover image available System-on-a-chip design and test / by Rajsuman, Rochit. Publication: Boston, [Mass.] : Artech House, 2000 . xiii, 277 p. : Date: 2000 Availability: No items available: Add to cart (remove)
	9.	No cover image available System-on-chip test architectures nanometer design for testability / Publication: Amsterdam ; \| Boston : Morgan Kaufmann Publishers, 2008 . xxxvi, 856 p. : Date: 2008 Availability: No items available: Add to cart (remove)
	10.	No cover image available Verification techniques for system-level design by Fujita, Masahiro, Publication: Amsterdam ; \| Boston : Morgan Kaufmann Publishers, 2008 . viii, 240 p. : Date: 2008 Availability: No items available: Add to cart (remove)
	11.	No cover image available VLSI test principles and architectures design for testability / Publication: Amsterdam ; \| Boston : Elsevier Morgan Kaufmann Publishers, 2006 . xxx, 777 p. : 25 cm. Date: 2006 Availability: No items available: Add to cart (remove)
	12.	No cover image available RF measurements for cellular phones and wireless data systems by Scott, Allan W. Publication: Hoboken, N.J. : IEEE : \| Wiley & Sons, 2008 . xx, 503 p. : Date: 2008 Availability: No items available: Add to cart (remove)
	13.	No cover image available Power-constrained testing of VLSI circuits by Nicolici, Nicola. Publication: Boston : Kluwer Academic Publishers, 2003 . xi, 178 p. : Date: 2003 Availability: No items available: Add to cart (remove)
	14.	No cover image available CTL for test information of digital ICs by Kapur, Rohit. Publication: Boston : Kluwer Academic Publishers, 2003 . ix, 173 p. : Date: 2003 Availability: No items available: Add to cart (remove)
	15.	No cover image available ESD failure mechanisms and models / by Voldman, Steven H. Publication: Chichester, West Sussex, U.K. ; \| Hoboken, NJ : J. Wiley, 2009 . xxiv, 384 p. Date: 2009 Availability: No items available: Add to cart (remove)
	16.	No cover image available Design for at-speed test, diagnosis, and measurement Publication: Boston : Kluwer Academic, 2000 . xvii, 239 p. : Date: 2000 Availability: No items available: Add to cart (remove)
	17.	No cover image available Essentials of electronic testing for digital, memory, and mixed signal VLSI circuits by Bushnell, Michael L. Publication: New York : Kluwer Academic, 2002 . xviii, 690 p. : Date: 2002 Availability: No items available: Add to cart (remove)
	18.	No cover image available Wafer-level testing and test during burn-in for integrated circuits by Bahukudumbi, Sudarshan. Publication: Boston : Artech House, 2010 . xv, 198 p. : Date: 2010 Availability: No items available: Add to cart (remove)
	19.	No cover image available System-on-a-chip design and test / by Rajsuman, Rochit. Publication: Boston, [Mass.] : Artech House, 2000 . xiii, 277 p. : Date: 2000 Availability: No items available: Add to cart (remove)
	20.	No cover image available System-on-chip test architectures nanometer design for testability / Publication: Amsterdam ; \| Boston : Morgan Kaufmann Publishers, 2008 . xxxvi, 856 p. : Date: 2008 Availability: No items available: Add to cart (remove)

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